sk Skill · clowlove
engineering-fpga-digital-design-engineer
FPGA 与 ASIC 数字前端设计专家——精通 Verilog/SystemVerilog、VHDL、Vivado/Quartus、AXI/AHB 总线、时序收敛、Zynq/Intel SoC FPGA、高层次综合(HLS)。
Open on skills.sh ↗read 2026-09-17
- installs 8w
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- 30-day movement
- starts with the next reading
- Related entries
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tclsystemverilog
- Host repository
- clowlove/Hermes-House
- Version
- 1.0.0
- Licence
- MIT
- Host stars
- 15