sk Skill · phamcuong21478
vsynth
Synthesize a Verilog module or full IP with Vivado and report resource utilization, Fmax, and power
Open on skills.sh ↗read 2026-09-15
- installs 8w
- 0
- 30-day movement
- starts with the next reading
- Related entries
- 1
- Connections
- 5
tclmarkdownbashSystemVerilog
- Host repository
- phamcuong21478/rtl-skills
- Allowed tools
- Read, Write, Bash, Grep, Glob
- Host stars
- 14
- Host language
- SystemVerilog