sk Skill · phamcuong21478
vtestgen
Scaffold a Makefile-driven, CPU-bus-controlled testbench project for an IP and generate a comprehensive set of self-checking testcases, validate each with make, and write a testcase list
Open on skills.sh ↗read 2026-09-15
- installs 8w
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- 30-day movement
- starts with the next reading
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markdownbashSystemVerilog
- Host repository
- phamcuong21478/rtl-skills
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- SystemVerilog