pyslang-verilog-context

Use pyslang-mcp for compiler-backed Verilog and SystemVerilog context. Trigger this skill for RTL, HDL, Verilog, SystemVerilog, module, interface, package, .sv, .svh, .v, .vh, or .f filelist analysis, review, debugging, coding, refactoring, hierarchy inspection, diagnostics triage, symbol lookup, include/define investigation, and design-unit summaries. Skip it for unrelated languages or trivial text searches where…